1. Field of the Invention
The present invention relates to a data processing apparatus and a data processing method for accessing a plurality of memories in parallel. The memories are used for storing data such as an image data and the like.
2. Description of the Related Art
A data processing apparatus using a data transfer bus is noted in Japanese Laid Open Patent Applications JPA-Heisei 3-163671, JP-A-Heisei 3-176754, JP-A-Heisei 6-195313, JP-A-Heisei 8-335204 and 3P-A-Heisei 9-223103. A data processing apparatus using a DMA controller is noted in Japanese Laid Open Patent Application JP-A-Heisei 9-223103. In this data processing apparatus, when a CPU accesses a memory, the DMA controller is set at a bus waiting state. In this data processing apparatus, when the DMA controller executes a DMA transfer, the CPU is set at the bus waiting state.
A data processing apparatus having a bus arbitration circuit is noted in Japanese Laid Open Patent Application JP-A-Heisei 9-223103. This bus arbitration circuit uses a plurality of system buses to accordingly arbitrate a right of using a bus. This bus arbitration circuit, when a bus request signal indicative of a request to use a system bus is generated, outputs a response signal corresponding to the bus request signal that serves as a bus grant signal. The right of using the bus is arbitrated based on the bus grant signal.
An object of the present invention is to provide a data processing apparatus and a data processing method which can reduce an occurrence of a bus open waiting state to thereby improve data processing speed.
Another object of the present invention is to provide a data processing apparatus and a data processing method in which a plurality of
CPUs, each accessing a memory, can mutually recognize data updates in the memories.
In order to achieve an aspect of the present invention, a data processing apparatus is provided with a plurality of processors, a plurality of memories, a memory bus selector and a control unit. The plurality of memories are accessed by the plurality of processors. The memory bus selector selects an access route between one of the plurality of processors and one of the plurality of memories. The control unit instructs the access routes to the memory bus selector based on a transfer request from the plurality of processors.
In the above, a data processing apparatus is provided with a plurality of system buses which connect the plurality of processors to each memory bus selector, respectively. The memory bus selector selects the access route based on an instruction from the control unit.
In the above, a data processing apparatus is provided with a parallel input-output unit connecting the plurality of processors and the control unit in parallel.
In the above, a data processing apparatus is provided with a serial interface unit connecting the plurality of processors and the control unit in serial.
In order to achieve an aspect of the present invention, a data processing apparatus is provided with a processor, a memory control unit, a plurality of memories and a plurality of memory bus selectors. The plurality of memories is accessed by the processors and the memory control unit. The memory bus selector selects an access route between the processors and one of the plurality of memories and between one of the memory control unit and one of the plurality of memories. The memory control unit instructs the access routes to the memory bus selector based on a request of the processors.
In the above, a data processing apparatus is provided with a plurality of system buses which connect the processors and the memory control unit to the memory bus selector. The memory bus selector selects the connection based on an instruction from the memory control unit.
In order to achieve an aspect of the present invention, a data processing apparatus is provided with a first and second system buses, a processor connected to the first system bus, a memory control unit connected to the processor, a plurality of memories, a plurality of memory bus selectors and a memory control unit. Each of the memory bus selectors is connected to the first and second system buses and a corresponding one of the plurality of memories and connects the corresponding memory to one of the first and second system buses in response to an instruction. The memory control unit generates a first instruction to a first one of the memory bus selectors in response to a first request from the processor such that the first memory bus selector selects the first system bus to allow the processor to access one of the plurality of memories corresponding to the first memory bus selector.
In the above, the memory control unit generates second and third instructions to the second and third memories of memory bus selectors in response to second and third requests from the processor. In response to the second and third instructions, the memory control unit reads data from the second memory via the second memory bus selector and the second memory bus and the memory control unit stores the data to the third memory via the third memory bus selector and the third memory bus.
In the above, a data processing apparatus is provided with a buffer.
In the above, the memory control unit generates the second and third instructions to the second and third memories of memory bus selectors in response to the second and third requests from the processor such that the memory control unit transfers data from the second memory to the buffer via the second memory bus selector and the second memory bus and the memory control unit transfers the data from the buffer to the third memory via the third memory bus selector and the third memory bus.
In order to achieve an aspect of the present invention, a method of accessing a plurality of memories selects a system bus between one of the plurality of processors and one of the plurality of memories. Furthermore, the method transfers data between the processor and the memory via the selected system bus.